The present invention relates generally to the field of semiconductor technology, and more particularly to the formation of fins used in fin field effect transistor (finFET) devices.
In the manufacture of integrated circuits, there is a continuing desire to fit more semiconductor devices and circuits on semiconductor wafers. The drive for miniaturization and increasing circuit density is driven by a number of factors, including device speed, as denser circuits are closer together for fast communication, wafer utilization (more circuits per wafer) and potential semiconductor chip cost reduction as the number of semiconductor chips per wafer increase.
One manufacturing method for creating wafers and semiconductor chips with the ability to aide in miniaturization is use of silicon-on-insulator (SOI) wafers. SOI wafers provide layers of silicon separated by a buried insulation layer such as silicon dioxide. In addition to providing opportunities for additional wafer real estate, SOI wafers provide the opportunity for improved electrical performance, such as lower parasitic capacitance and reduced resistance to latch up. The semiconductor devices fabricated in the layer of silicon, which is above a layer of electrical insulating material such as SiO2, experience improved semiconductor device isolation and performance. SOI wafers may be created by several processes including oxygen implantation using a high temperature anneal process which may be called Separation by Implantation of Oxygen (SIMOX), Separation by Implantation Of Nitrogen (SIMON), or bonding two wafers together, one of which has an insulating or oxide layer forming a buried oxide layer (BOX) or other dielectric material layer sandwiched between the wafers.
Another method used to increase circuit density on a wafer and improve performance is the development of fin field-effect transistors (finFETs) which utilize three dimensions for device formation. In finFET technology, a thin, vertical fin is used for the conducting channel between the source and drain. The fin is wrapped by a gate creating a wrap-around gate for a channel structure providing better electrical control of the channel and reduced short channel effects. FinFETs may be constructed on a bulk silicon substrate or, in some cases, may be formed on a SOI wafer.